Simplified Data Paths for General-Purpose Registers
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Current general-purpose register (GPR) implementations entail a GPR file (structure) which accommodates multiple read and write accesses per cycle. The multiple writes are associated with pipelined (high performance) operations where both the ALU (arithmetic logic unit) and memory bus are writing the GPRs concurrently. The multiple reads per cycle are associated with: a. IBM System/370 address generation which may require multiple concurrent register access. b. Register - Register arithmetic instructions. An analysis of register accessing requirement shows that the GPR file can be simplified if a load buffer is created which contains GPR registers that have been loaded from memory and not yet modified. Since modification of the registers requires an ALU operation, the GPR file is written only as the output of the ALU.