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Programmable Clock Divider

IP.com Disclosure Number: IPCOM000044306D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05

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Nahata, P [+details]


A technique is described whereby a counter and a digital magnitude comparator are utilized to divide a single base clock frequency into multiple clock frequencies for circuit application which require multiple clock frequencies derived from a single clock. At the beginning of the operation, counter 10, as shown in Fig. 1, is cleared and flip-flop 11 is reset. Counter 10 is incremented by "1" at the first leading edge 13 of the clock signal 12 shown in Fig. 2. The contents of counter 10 are then compared with the setting of comparator 14. If both values are equal, then A=B output 15 of the comparator becomes active and causes an output from flip-flop 11. If the compared values are not equal, A>B output 16 becomes active and flip- flop 11 stays reset.