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Anticipatory Carry Incrementor Disclosure Number: IPCOM000044310D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05

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Awsienko, O Nahata, P [+details]


A technique is described whereby a simple circuit is used to increment an address by four in one gate delay cycle utilizing a carry anticipatory approach. Therefore, it is possible to complete an entire full word incrementing operation in one cycle rather than requiring multiple cycles. When master and slave direct memory access (DMA) concepts are used in transferring data from one input/output bus unit (IOBU) to another, the second IOBU supplies the first IOBU with the memory starting address and the length of the transfer data. Due to misalignment in the master and slave addresses, adjustments are required to allow addresses on storage lines. During the first data cycle, the address is placed on the address lines as they are received.