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Two-Dimensional Layout of Single-Ended Cvs Trees in Masterslice and Means for Realizing a Compact Master Image Layout Using Two-Dimensional Diffusion Wiring Disclosure Number: IPCOM000044335D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05

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Hauge, PS Montoye, RK [+details]


The high functional density achievable with cascode circuit technology poses a challenge for designers to find circuit layouts which realize these high densities while still being wirable. In masterslice designs, single-ended cascode voltage switch (SCVS) circuits in particular are difficult to wire. This article describes a method to lay out SCVS circuits in a natural, two-dimensional array of transistors which attains high functional density and a means of using diffusion wiring also in two dimensions to enhance wirability. In the logical design of SCVS circuits, series/parallel (SP) orderings of transistors are encountered. Such circuits are more naturally realized as two-dimensional layouts than linear, one-dimensional layouts.