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Browse Prior Art Database

Associative Register Assignment Stack

IP.com Disclosure Number: IPCOM000044355D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05

Publishing Venue

IBM

Related People

Authors:
Emma, PG Pomerene, JH Puzak, TR Rechtschaffen, RN Sparacio, FJ [+details]

Abstract

A relatively small Associative Register Assignment Stack (ARAS) can be used to verify entries in an Operand History Table (OHT) at I-fetch time. This would preclude superfluous cache-bus cycles, eliminate the need for an AGEN cycle, and reduce the bandwidth requirement on the register set. An ARAS is an LRU (least recently used) stack of entries, where each entry consists of the pair {Instruction Address, Name of Register used for AGEN}. Each instruction that has a memory source operand will make an entry in the table, e.g., if the instruction L R1,10(R2,0) is fetched from location 30, it will make the entry {30,2} in the ARAS since R2 is used to generate the source operand address. On subsequent fetches of this instruction, the instruction address (30) is used as an associative key on the ARAS.