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Page Mode Operation of Dynamic Graphics Memory Disclosure Number: IPCOM000044376D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05

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Dean, ME Kummer, DA Saenz, JA [+details]


A technique is described whereby a video system, operating in page mode, provides an increase in data bus bandwidth without increasing the size of the data bus. A dual-port memory structure is accessed in synchronism with character tracing cycles of a cathode ray tube (CRT) to provide multiplexed accesses of the CRT and central processing unit (CPU). The dual-port memory structure allows two character clock cycles to coincide with two memory access cycles; one to read character dot information to the CRT controller (CRTC) and the other to provide accessibility to the CPU. In order to display 256 different characters with 16 background colors, eight foreground colors along with blinking attribute at each alphanumeric character, 16 bits of data are required each character clock time.