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Improved Cache to Instruction Buffer System Organization

IP.com Disclosure Number: IPCOM000044406D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05

Publishing Venue


Related People

Capozzi, AJ Kelley, WJ Wassel, ER [+details]


An improved cache to buffer system can be organized by utilizing an intermediate buffer as the source of the instruction stream. This system obtains the benefits of an I-cache/D-cache organization without implementing the I-cache. To fully exploit the intermediate buffer 11 to instruction buffer (I-buffer) 12 implementation, it is desirable to utilize the widest possible data path available at buffer 11. Since this is a read-only path, the logic is minimal, and represents an extra load on the buffer 11 to cache 13 data path. There are many existing algorithms and de sign approaches to instruction prefetching and branch prediction. Proper selection of the implementation technique will ensure minimum interruption to the instruction stream although the buffer 11 can be expected to have a slower access time than cache 13.