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Browse Prior Art Database

Method of LSI Personalization After Resetting

IP.com Disclosure Number: IPCOM000044423D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05

Publishing Venue

IBM

Related People

Authors:
Iida, H Morimoto, Y [+details]

Abstract

This article describes a method for personalizing a plurality of large- scale integration circuits (LSIs) connected to a data bus of a processing unit, e.g., a microprocessor. Each of the LSIs is serially personalized by loading a personalization data or LSI address into its own personalization register through the data bus. The drawing shows a scheme of personalization in which LSIs (LSI0 - LSIn) are connected in parallel with a data bus 10 and a write signal line 12 but in series with a reset line 14. The data bus 10, the write signal line 12 and the reset line 14 are all connected to a microprocessor (not shown). Upon initialization, the microprocessor generates a power-on-reset signal on the reset line 14 to enable the first LSI (LSI0) to be personalized.