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# G-Map, a Trinary Logic Minimization Aid

IP.com Disclosure Number: IPCOM000044440D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 58K

IBM

## Related People

Grimes, DW: AUTHOR

## Abstract

A trinary logic design aid is described that facilitates minimization of the hardware implementation of trinary logic functions using two or more trits (trinary digits). Trinary logic uses three logic levels (0, 1, 2) instead of the two logic levels of binary logic. This provides more opportunity for combinations, so the number of hardware circuits required to implement a given function is reduced. Also, the number of signal lines is reduced because three states exist for each trit as opposed to two states for each bit. Therefore, trinary logic requires fewer interconnections than binary logic to perform an equivalent logic function. For example, a four-trit function has 81 possible states, while a four-bit function has only 16 states. A method for binary logic reduction is described by M.

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G-Map, a Trinary Logic Minimization Aid

A trinary logic design aid is described that facilitates minimization of the hardware implementation of trinary logic functions using two or more trits (trinary digits). Trinary logic uses three logic levels (0, 1, 2) instead of the two logic levels of binary logic. This provides more opportunity for combinations, so the number of hardware circuits required to implement a given function is reduced. Also, the number of signal lines is reduced because three states exist for each trit as opposed to two states for each bit. Therefore, trinary logic requires fewer interconnections than binary logic to perform an equivalent logic function. For example, a four-trit function has 81 possible states, while a four-bit function has only 16 states. A method for binary logic reduction is described by M. Karnaugh, "The Map Method for Synthesis of Combinational Logic Circuits," Communications and Electronics, 593-599 (November 1953). This method is known as the Karnaugh Map or K-map and provides a very convenient way of visualizing various relationships useful in logic design by making the prime implicants of a logic equation correspond to patterns familiar to the eye. The K- map method, however, breaks down when applied to trinary logic minimization having three or more variables. Fig. 1A is a two-variable Grimes Map or G-map with the corresponding truth table shown in Fig. 1B. The visual pattern created by plotting the function f1 on the G-map allows one to recognize the function as f1 = A2 + B2. This result is similar to that afforded by the K-map approach; however, the addition of another trit variable complicates matters. Fig. 2A is a three-trit map using the K-map method. As can be seen, no easily recognizable pattern is evident. To create a G-map, the map in Fig. 2A is divided into three 9- piece squares connected by imaginary hinges. Referring to Fig. 2B, the center 9- piece square is rotated down and to the left on its left hinge and the right 9-piece square is not rotated but is c...