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Coordinated Machinery for Performance in Automatic Computing

IP.com Disclosure Number: IPCOM000044463D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06

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Chen, TC [+details]


This article describes architecture for a large scientific supercomputer with very unconventional instruction structure, aimed at maximal use of available hardware, parallel constructs for extra performance, provision for new schemes to enhance accuracy, privacy, synchronization and extreme compactness of machine code. This supercomputer derives its power by a consistent application of the new 'compute and update' operation principle. An entire floating-point computation innerloop, equivalent to 8 or more IBM System 370 instructions, can be contained in one compact 'superinstruction' of bits, and can be executed at the pipelined rate of one full iteration per CPU cycle. This is more than twice as fast as its nearest scalar (i.e.