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Optimizing Overlay in Multilevel Optical Lithography

IP.com Disclosure Number: IPCOM000044471D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06

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Herd, H Jacobowitz, L [+details]


The presented process provides optical alignment patterns on zero-level silicon wafers used in manufacturing integrated circuit chips. The zero-level patterns are used for subsequent photolithographic processing instead of conventional level-to-level alignment marks. Construction of integrated circuit chip patterns on silicon wafers requires precisely aligned vertical structures containing intricately patterned multiple layers. To reproducibly achieve layer-to-layer optical registration, two requirements must be satisfied: (1) creation and preservation of high optical contrast alignment marks and (2) a means of referencing, calibrating, and correcting for hot-process induced wafer dimensional changes. The following process achieves these goals: 1.