Browse Prior Art Database

Diode Doubling

IP.com Disclosure Number: IPCOM000044515D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06

Publishing Venue

IBM

Related People

Authors:
Reynolds, CB [+details]

Abstract

Diode doubling for high drive applications increases the effectiveness of pulldown devices, improving both performance and density. In conventional NMOS circuits, the maximum drive capability is gated by the area required for the output-stage pulldown devices (particularly for wide NOR, NAND and AOI/OAI configurations). The addition of an enhancement-mode device (EMD) or zero threshold device (ZVT) 11, as shown, allows the initial stage pulldowns (devices 2-5) to assist in the discharge of output capacitance - reducing the effective width-to-length ratio required of devices 7-10. This technique is employed in enhanced clock driver designs, where it was shown, via circuit simulation, to improve falling delays by approximately 20%.