High-Frequency LSSD Clock Generator
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
A technique is described whereby a high-frequency clock generator is designed for compatibility with level sensitive scan design (LSSD) technology. The design provides the following significant features: 1. Clock generation on a single chip greater than 20 MHz 2. Full LSSD compatibility 3. High testability (99.85 percent) 4. Testability is achieved with automatic test pattern generators 5. Clock symmetry is independent of oscillator symmetry 6. Minimum variation in clock pulse width 7. No special modules or circuits are required. The functional operation of the clock generator, as shown in the block diagram of Fig. 1, is to achieve precise control over the pulse width of the clock.