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High Yield Anneal for Gallium Arsenide Wafers

IP.com Disclosure Number: IPCOM000044556D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06

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Robbins, GJ [+details]


This is a method of increasing yields of gallium arsenide (GaAs) wafers by tailoring the process to the particular properties of individual wafers as opposed to blanket process specifications. The proposed method is to individually characterize wafers and define implants specific to each wafer and to specific areas upon a wafer. The GaAs MESFET (metal Schottky FET) device has practical, high performance applications in future digital integrated circuits, but suffers from switching threshold voltage (VTH) process variations which limit yield and cause performance tradeoffs. This is due to variations in wafer background impurities, sensitivity of VTH as square of chemical depth, proportional to channel doping and Schottky diode forward voltage variations.