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Integrated Circuit Test Adapter

IP.com Disclosure Number: IPCOM000044595D
Original Publication Date: 1984-Oct-01
Included in the Prior Art Database: 2005-Feb-06

Publishing Venue

IBM

Related People

Authors:
Grace, AH Hefter, GR Rivera, M [+details]

Abstract

The device disclosed helps establish the flexibility needed to test new, as well as standard, integrated circuit package styles without extensive test hardware rebuild. The adapter 1 in Fig. 1 can be constructed out of a modified FR-4 epoxy laminate with at least one buried layer of circuitry 2. This material was selected based on its high temperature- and moisture-resistant characteristics, thus making it suitable for a wide range of stress applications. The circuitry 2 (or "trace") runs between a contact pad 3 at the point where the sample is to be inserted and a plated-through hole 4 in the dual/in-line pattern. As shown in Fig. 2, there is a recess 5 to minimize slippage of the device. There is also a cut-out 6 in the adapter beneath the device to prevent cold-spot condensation in temperature humidity environments.