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AN SiO-PARYLENE COMPOSITE INSULATOR FOR IMPROVED DEFECT LEVELS IN LARGE-SCALE INTEGRATED CIRCUITS

IP.com Disclosure Number: IPCOM000044602D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06

Publishing Venue

IBM

Related People

Authors:
Baker, JM Magerlein, JH Palmer, MJ [+details]

Abstract

Composite silicon monoxide/parylene insulator films reduce the defect levels in large-scale integrated circuits to defect densities significantly below those for single-layer insulating films deposited on substrates near room temperature. This composite insulator has better thermal cycling characteristics than an SiO layer of equal thickness and the adhesion of the composite is superior to that of parylene alone. The figure shows how pattern area 1 and identical pattern area 2 are opened, without allowing defect 3 to open a false pattern. This composite insulator consists of a thin layer of deposited SiO followed by a thin layer of parylene. The SiO can be patterned by well-established lift-off techniques.