Circuits for the Synchronization of Asynchronous Input Signals
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
This article describes new signal validity detection circuits (SVDC). These circuits reduce the probability of synchronization failure of bus control units to acceptable levels. The block diagram is shown in Fig. 1. The output of the detection circuits (DET) is 1 in a normal situation to allow the outputs of the bus control unit to be passed to the next stage at the rising edge of the clock. When the input signal transition is very close to the falling edge of the clock and the input flip-flops may get into the metastable state, DET will change to 0 to prevent certain outputs of the bus control unit (controlled by the bus control logic) from being passed to the next stage at the rising edge of the clock. The implementations of the detection circuits are described here.