Browse Prior Art Database

Serial-Access Page-Mode Memory

IP.com Disclosure Number: IPCOM000044622D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06

Publishing Venue

IBM

Related People

Authors:
Scheuerlein, RE [+details]

Abstract

This article describes a method of reducing the cost of large backing stores by eliminating the column decoder and associated support circuitry. The rows of sense amplifiers (SAs) function as a serial-access memory by the addition of very little circuitry. Since the backing store applications require the transfer of blocks of data "pages", the system can accept the reduced flexibility of the memory. The memory chip structure can still provide adequate data rates because the cycle time for the sequential data access is much shorter than standard cycle times. The serial-access page-mode memory disclosed here can be designed with an eight-device SA without a column decoder, as shown in the memory design. Far fewer decoders, i.e., block decoders 10, serving to select blocks of sense amplifiers, would be needed.