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Browse Prior Art Database

Bus Arbiter With Selectable Rotating Highest Priority

IP.com Disclosure Number: IPCOM000044643D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06

Publishing Venue

IBM

Related People

Authors:
Malmquist, CA Wilson, JD [+details]

Abstract

This arbitration scheme establishes a sequence to handle changes in real time demands for bus traffic. This scheme allows subunits with lower priority a guaranteed percentage of high priority and also prevents dead cycles of arbitration associated with simple rotating high priority arbiters. The standard arbiter 6 has a fixed priority in descending order and has been improved so that devices with lower priority, with critical time dependencies, may have highest priority a certain percentage of the time, when arbitration is possible. In this example, there are eight subunits that would be requesting access to the bus. Some of these subunits may need to have highest priority at least part of the time. The new arbiter circuit achieves this rotating priority in the following manner.