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Schottky Diode Butting Against Recessed Oxide Isolation

IP.com Disclosure Number: IPCOM000044661D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06

Publishing Venue

IBM

Related People

Authors:
Jambotkar, CG [+details]

Abstract

In many integrated circuit designs, the chip area can be appreciably reduced if Schottky anodes could be butted against recessed oxide isolation (ROI) walls. Two impediments to this approach are the probable occurrence of parasitic low-barrier Schottky diode at the periphery and excessive leakage and reduced breakdown voltage due to charge in the ROI. This article discloses a method for obtaining Schottky anodes butted against the ROI while being protected by extremely small, self-aligned, P- type guard rings at their peripheries. Two methods of obtaining butted Schottky anodes are described so as to broaden the applicability of the disclosed procedure to existing technology. Referring to Fig. 1, the procedure begins with formation of Nsubcollector 4 and N-epi 6 on a P- substrate.