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CMOS Lssd Shift Register Latch

IP.com Disclosure Number: IPCOM000044673D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06

Publishing Venue

IBM

Related People

Authors:
Piro, RA Sporck, FR [+details]

Abstract

This article describes a complementary metal oxide semiconductor (CMOS) latch which can be easily implemented in a master slice design without the use of transfer gates, thereby enhancing testability. The diagram shows a two-stage polarity-hold version in which the memory function of the latch is performed by standard CMOS cross-coupled pairs, devices T1 through T4 in the first stage and T13 through T16 in the second. The state of the latch is changed by pulling down either one side or the other. During this transition, one of the pairs of n-channels turns on and overpowers the p-channel pullup of the latch, so as to pull the node down. The output can be taken from either side of the latch and be used to drive a buffer circuit, as shown in the diagram.