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Clocked CMOS Logic Using Triple Gate FETs

IP.com Disclosure Number: IPCOM000044901D
Original Publication Date: 1983-Jan-01
Included in the Prior Art Database: 2005-Feb-06

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Archer, DW [+details]


A clocked CMOS NAND circuit is disclosed which employs a triple-gate P channel FET device 40 and a triple-gate N channel FET device 42 which operate on the same principle as do the multiple gate FET devices described in the preceding article.