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Improved Cycle Rate of Main Memory Write Functions Disclosure Number: IPCOM000045000D
Original Publication Date: 1983-Jan-01
Included in the Prior Art Database: 2005-Feb-06

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Grimes, DW Martinez, PL [+details]


A technique is described to improve system performance in Memory Write Cycle operations. Memory technologies are restricted by their cycle time specifications (i.e., their cycle time cannot be faster than specified). During consecutive memory cycles, the second cycle cannot be allowed to commence until the specified cycle width of the first cycle has been completed properly. Minimum cycle time specifications insure adequate recovery time for the memory modules' circuits between accesses. System performance is constrained by these memory requirements.