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Spiral Read Write Architecture for Processor Controlled Diskette Unit

IP.com Disclosure Number: IPCOM000045002D
Original Publication Date: 1983-Jan-01
Included in the Prior Art Database: 2005-Feb-06

Publishing Venue


Related People

Billington, JT Payne, GW [+details]


Multiple track data transfers followed by one interrupt request are effected with a single command from an IBM Series/1 processor to a diskette unit. Heretofore, a typical operation resulting from a single command issued by the Series/1 to a Model 4966 Diskette Magazine unit, for example, allowed only a single track, single head data transfer followed by an interrupt.