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A method is described for using a processor bus holdover register to do conditional branching after the data has been gated off.
English (United States)
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Processor Bus Holdover for Conditional Processor Bus Branches
A method is described for using a processor bus holdover register to do
conditional branching after the data has been gated off.
In Fig. 1, the read-only storage address register (ROSAR) is clocked every
Time D. In order to branch, conditions from the processor bus (PB) must be held
over from Time BC to Time D. The processor bus holdover register is clocked
with the Destination Pulse (Time C) and is gated to the processor bus from just
before Gate Source to PB goes away (so there will not be any glitch on the
processor bus) until just after Clock ROSAR goes away (so the processor bus
will be valid while the ROSAR is being clocked).
In Fig. 2, the processor bus is clocked into the processor bus holdover
register 1 with the Destination Pulse. AND circuit 2 maintains valid data on the
processor bus long enough for the conditional branch controls 3 to resolve the
new address to be clocked into the ROSAR 4.
Fig. 3 shows several possible two-way and four-way branches. For each of
the eight decodes, ROSAR bits 10 to 13 are turned on if the listed processor bus
bits are on.
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