Browse Prior Art Database

Logic Design Simulator using APL

IP.com Disclosure Number: IPCOM000045060D
Original Publication Date: 1983-Jan-01
Included in the Prior Art Database: 2005-Feb-06

Publishing Venue

IBM

Related People

Authors:
Slishman, GR [+details]

Abstract

The characteristic component of a Level Sensitive Scan Design (LSSD) is the Shift Register Latch (SRL), consisting of two D-latches, L1 and L2. Non-overlapping clocks, denoted C and B, control the L1 and L2, respectively. Since an L1 latch is never a function of L1s, and an L2 latch is never a function of L2s, adequate clock separation precludes signal races.