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Method for Forming Vertical Walled Trenches in Silicon Substrates Using Reactive Sputter Etching

IP.com Disclosure Number: IPCOM000045068D
Original Publication Date: 1983-Jan-01
Included in the Prior Art Database: 2005-Feb-06

Publishing Venue

IBM

Related People

Authors:
Lechaton, JS MacPherson, CC [+details]

Abstract

Deep trenches are used in VLSI to isolate the individual devices. The trenches may be formed by reactive sputter etching. To increase the device density and reduce the mask set, a blanket subcollector diffusion or implant is used and then patterned by the deep trench etching after the N- epitaxy is grown. Normally during reactive ion etching there is an enhanced etching at the N+ sublayer. This is true particularly in both CC1(2)F and CBrF(3)/O(2)etching. The figure schematically depicts this situation wherein the left side shows the undesired enhanced etching and the right side shows the desired etching result. In order to reduce the windage in the photoresist pattern and improve any filling techniques for the trenches, It is also important to have vertical walls in the mask SiO(2) layer as at the right side of the figure.