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Reduction of Bit Line Capacitance

IP.com Disclosure Number: IPCOM000045077D
Original Publication Date: 1983-Jan-01
Included in the Prior Art Database: 2005-Feb-06

Publishing Venue

IBM

Related People

Authors:
Shepard, JF [+details]

Abstract

The speed of random-access memory (RAM) circuits may be limited by large bit line capacitance. The primary source of this capacitance may be better understood by reference to Fig. 1. Fig. 1 illustrates the vertical cross-section of a memory device of a RAM wherein the P- monocrystalline silicon substrate 10 has N+ storage capacitor region 12 and N+ bit line 14 formed therein. Insulator layers 16 and 18 of silicon dioxide and silicon nitride, respectively, cover the major surface of substrate 10. An arsenic glass layer 20 covers a portion of the bit line region 14. This layer 20 had been formed by chemical vapor deposition and heated to form the bit line region 14 by outdiffusion.