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A recessed oxide isolated enhancement/depletion MOSFET device is described. The process eliminates possible contamination of the gate silicon dioxide dielectric by the resist layer in the depletion device.
English (United States)
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Buried Contact Depletion Device Process
A recessed oxide isolated enhancement/depletion MOSFET device is
described. The process eliminates possible contamination of the gate silicon
dioxide dielectric by the resist layer in the depletion device.
A monocrystalline P- silicon substrate 10 is provided with regions of recessed
oxide isolation 11 and P+ junction isolation thereunder which isolate surface
regions of the silicon substrate from one another. A gate dielectric oxide layer 12
is formed upon the depletion and enhancement regions. A boron ion
implantation is used for voltage threshold adjustment and forms P region 13. A
layer 14, of between about 25 to 100 nanometers of polycrystalline silicon, is
deposited over the surface. The layer 14 may be N+ doped or left undoped.
Lithography and etching techniques are used to form resist layer mask 15
covering the planned enhancement device areas. Ion implantation is used to
form N region 16 in the depletion region. The N dopant may be arsenic or
phosphorous. The result of these steps is shown in Fig. 1. The resist layer 15 is
removed by etching.
Lithography and etching techniques are used to form buried
contact mask resist layer 17. The openings in the mask are at the
designated locations of the buried contacts to the depletion devices.
The poly-crystalline silicon layer 14 and gate dielectric layer 12
are removed by etching down to the monocrystalline silicon surface,
as shown in Fig. 2. The resist layer 17 is remove...