Low Power Electrical Level Sensitive Scan Design Latch
Original Publication Date: 1983-Jan-01
Included in the Prior Art Database: 2005-Feb-06
One effect of using LSSD (*) latches, in addition to the cell area loss, is the dissipation of additional power when the testing mode is completed and the product is in normal system mode. This article proposes an LSSD latch implementation which effectively depowers LSSD latches to dissipate 1/7 of normal SRL (Shift Register Latch) power when used in a data path (Fig. 1) and consumes no power when in the clock path (Fig. 2) during normal system state.