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The diagnosability of logic circuits can be improved by converting some internal lines into externally observable test points.
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Method for Sampling Test Points in Logic Circuits
The diagnosability of logic circuits can be improved by converting some
internal lines into externally observable test points.
Within an LSSD (level sensitive scan design) - structured design, a shift
register latch (SRL) consisting of an L1 latch with 2 system clocks and an L2
latch affords a relatively inexpensive means of sampling two test points while
maintaining the normal SRL functions of system latch and scan. The nodes in
the diagram labeled TP1 and TP2 represent the two test points. With all system
and shift clocks off, raising and lowering the Sample Clock line captures the state
of TP1 in the L1 latch and the state of TP2 in the L2 latch.
Scan-out to the shift register output PO is used to observe the captured
states. If the scan-out cycle begins with a Shift B Clock pulse, the contents of L1
and hence the state of TP1 will be observed. Alternatively, if the scan-out cycle
begins with a Shift A Clock pulse, the contents of L2 and hence the state of TP2
will be observed.
If more than two test points are to be observed, additional SRLs structured as
shown must be used, one SRL for each two additional test points.
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