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Clock Signal Generator Disclosure Number: IPCOM000045191D
Original Publication Date: 1983-Feb-01
Included in the Prior Art Database: 2005-Feb-06

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Wisgo, GD [+details]


The circuit in Fig. 1 allows, for example, a Motorola 68B54 advanced data link control module 10 to be interfaced to an Intel bus. Control module 10 requires that all input/output (I/O) activity be synchronous with respect to a system E clock signal. When interfacing the controller 10 to an bus, a single level of data buffering is required to hold the read data during an I/O read cycle. For such conditions, buffer control logic introduces additional delay and results in lost data. This problem can be solved by extending the E clock signal for I/O cycles.