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The disclosed circuit is a high performance, low power NOR logic circuit. It has active pull-up and pull-down for good fanout capability.
English (United States)
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Push Pull Logic Circuit
The disclosed circuit is a high performance, low power NOR logic circuit. It
has active pull-up and pull-down for good fanout capability.
The network consisting of R2, T2 and T3 is a current mirror, where the role of
current source and biasing device alternates between T2 and T3, depending on
the input level. When both inputs are low, transistors T1 and T5, as well as
Schottky barrier diode (SBD) D3, are off. The current from R2 is directed through
D2 into the collector of T2, and a current mirror is set up between T2 and T3. T2
has twice the emitter area of T3, so that the collector current of T3 is half that of
the current in R2.
When an input goes high, T1 turns on. During the transition, D1 and D2 are
both off, allowing for active pull-down of the output. When the output reaches
about 0.8 volt, D3 turns on, and a current mirror is again set up between T2 and
T3. The collector current of T2 is twice that of R2, which pulls down the base of
T4 until clamped by T5. The emitter area of T2 is designed to be twice that of T3
so that R1 may be reduced, enhancing the up-going transition.
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