Static Latch with Multiple Input Ports
Original Publication Date: 1983-Feb-01
Included in the Prior Art Database: 2005-Feb-06
Fig. 1 depicts a general form of a shift register latch (SRL) in a TTL (transistor transistor logic) Masterslice. For a more detailed discussion of shift register latches (SRLs) and their employment in level sensitive scan design (LSSD), see the references.