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IP.com Disclosure Number: IPCOM000045413D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2005-Feb-07
Document File: 3 page(s) / 37K

IBM

## Related People

Finney, DW: AUTHOR

## Abstract

Performance of floating-point multiply and divide is enhanced and the microcode needed to perform that operation is simplified in conjunction with a carry save adder of the type described in U.S. Patent 4,110,832.

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Performance of floating-point multiply and divide is enhanced and the microcode needed to perform that operation is simplified in conjunction with a carry save adder of the type described in U.S. Patent 4,110,832.

A multiply operation is performed in a series of shifts and additions. First, the multiplier bit corresponding to the current cycle is checked for 0 or 1. If the bit equals 1, the partial product is shifted right 1 position and the multiplicand is added to form a new partial product. If the multiplier bit is 0, only the shift right is performed.

Similarly, a divide operation is performed as a series of shifts and subtractions. By storing the remainder in complemented form, the subtractions will actually become additions. The divide is accomplished by shifting the remainder left 1 bit position and first checking if the addition of the divisor to the complemented remainder would result in an error via the passive divide look-ahead circuitry.

If no error would occur, the addition is performed, but if an error is indicated, then only the shift is performed.

Increased performance is realized by generating both the result of the shift only (PS2, PC2) and of the shift and add (PS3, PC3) at the same time and using the condition to gate the correct result to the sum and carry latches.

The shift operation is accomplished in Fig. 1 by selecting the sum and carry pair and performing an addition with the data equal to 0 to form Presum 2 (PS2) and Precarry 2 (PC2).

For multiply PS2 Bit N=Sum Bit N-1+Carry Bit N

PC2 Bit N=Sum Bit N-1.Ca...