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Circuitry is described for aligning two operands for a floating point add or subtract operation more efficiently and using as few microwords as possible.
English (United States)
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Floating Point Operand Alignment
Circuitry is described for aligning two operands for a floating point add or
subtract operation more efficiently and using as few microwords as possible.
Before a floating point addition or subtraction may be performed, the
operands must be aligned. The characteristics of the two operands are
compared, and the fraction accompanying the smaller characteristic is shifted
right, with its characteristic increased by one for each hexadecimal digit shifted
until the two characteristics are equal.
In the circuitry shown in the drawing, the characteristics of operands A and B
are stored in two seven-bit registers 1 and 2 (Exp A and Exp B) which are used
as inputs to comparator 3 and ALU 4. A,B Register Control block 5 and ALU
Control block 6 are also provided. The fractions of the operands are stored in two
shift registers 7 and 8 (Fraction A and Fraction B) which are capable of shifting
right 4 bits (1 hexadecimal digit) per microcycle controlled by block 9.
The outputs of comparator 3 (A=B, A)B, and A<B) are used in conjunction
with the microcode to control shift registers 7 and 8, ALU 4 and the gating of the
incremented characteristic to the correct register. When the microcode control
"Align Operands" is issued and A>B is active, then controls are activated to shift
Fraction B right 1 hex digit, increment characteristic B by 1, and gate the ALU 4
output to the Exp B register 2. Similarly if A<B is active during the cycle, then the