Instruction Retry Mechanism for a Multimicroprocessor System
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2005-Feb-07
The instruction retry mechanism described herein consists of an instruction retry latch and a protocol between all microprocessors in the system. The instruction retry latch is set on power-up, on system reset or whenever there has been a successful instruction fetch from main storage. The instruction retry latch is reset whenever there has been an operand write and a successful write indication from main storage.