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Instruction Retry Mechanism for a Multimicroprocessor System

IP.com Disclosure Number: IPCOM000045455D
Original Publication Date: 1983-Mar-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Buonomo, JP Houghtalen, SR Losinger, RE Valashinas, JW [+details]

Abstract

The instruction retry mechanism described herein consists of an instruction retry latch and a protocol between all microprocessors in the system. The instruction retry latch is set on power-up, on system reset or whenever there has been a successful instruction fetch from main storage. The instruction retry latch is reset whenever there has been an operand write and a successful write indication from main storage.