Table Generator Test Generation Algorithm
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
This is a system of algorithms and heuristics designed to provide efficient and effective automatic test generation for VLSI (very large-scale integration) designs. Many test generators are limited to structures of not more than 4000 gates. This test generator can effectively provide full stuck-fault test generation on unpartitioned structures in excess of 30,000 gates.