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Table Generator Test Generation Algorithm Disclosure Number: IPCOM000045619D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07

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Butler, RW Cesa, LJ Godoy, HC Li, HH [+details]


This is a system of algorithms and heuristics designed to provide efficient and effective automatic test generation for VLSI (very large-scale integration) designs. Many test generators are limited to structures of not more than 4000 gates. This test generator can effectively provide full stuck-fault test generation on unpartitioned structures in excess of 30,000 gates.