The InnovationQ application will be updated on Sunday, May 31st from 10am-noon ET. You may experience brief service interruptions during that time.
Browse Prior Art Database

Parity Checking of PLA Implemented Counter

IP.com Disclosure Number: IPCOM000045685D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue


Related People

Boden, RC Pitchett, L [+details]


Fig. 1 illustrates symbolically an 8-stage binary counter withone parity stage, implemented in a conventional programmable logic array (PLA) comprising an AND array 10 and an OR array 11.