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Browse Prior Art Database

Parity Checking of PLA Implemented Counter

IP.com Disclosure Number: IPCOM000045685D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Boden, RC Pitchett, L [+details]

Abstract

Fig. 1 illustrates symbolically an 8-stage binary counter withone parity stage, implemented in a conventional programmable logic array (PLA) comprising an AND array 10 and an OR array 11.