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Multi Level Logic Testing Disclosure Number: IPCOM000045698D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07

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Hayward, M [+details]


A two-state logic array buried behind a multi-level logic input block on a complex integrated circuit module has heretofore been tested using special test pins providing access to the logic array, with the multi-level logic being separately tested using analogue methods. A macro equivalence scheme allows a single test procedure to be applied to both the two-state logic array and the multi-level logic input block. By this means, logic simulation and pattern generation can be applied to the input port of the module, saving the special test pins and avoiding time-consuming testing with two testers.