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Shared Cache in a Checkpoint Environment Disclosure Number: IPCOM000045734D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07

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Weiss, JA Willner, BE [+details]


In the figure, a four-way multiprocessing system is shown. The four central processing units (CPUs) are labeled CPU 1, CPU 2, etc. Each CPU has its own Store In Cache labeled Cache 1, Cache 2, etc. The IBM System/370 architecture is implemented under a checkpoint philosophy. A shared Store In Cache is implemented for lines which are used by more than one CPU. The ideas of checkpointing and shared cache are expanded on. The management of the shared cache is discussed in detail below.