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Scan Loadable Mode Registers for Multiple Processor, Multiple Architecture Systems

IP.com Disclosure Number: IPCOM000045807D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Callahan, RW Hughes, JE [+details]

Abstract

Mixed processor and/or architecture systems are known. In such systems, it would be advantageous to allow the master or service processor to control or reconfigure each processor, as required, in order that the system may achieve high availability and versatility. The main objectives of this capability are: 1. to gain high availability by allowing a service/master processor to turn off a failing processor and turn on a redundant processor or subunit, 2. to allow a service/master processor to instruct a failing 32 bit address architecture Processor to switch to 24-bit architecture and continue running if the failure occurred in the high-order addressing, and 3.