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Double Interlaced CCD with Buffered Transfer Gate

IP.com Disclosure Number: IPCOM000045837D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Carballo, RA Chung, PW Ghafghaichi, MB Pettigrew, MB Tzou, AJ [+details]

Abstract

This is a charge input and output technique for an SPS (serial-parallel serial) CCD (charge-coupled device) register. Unlike the most conventional SPS CCD register, this technique deals with charge inputting to and outputting from two selectable channels by buffering the charge transfers at both the serial to parallel and parallel to serial charge transfer stages.