Double Interlaced CCD with Buffered Transfer Gate
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
This is a charge input and output technique for an SPS (serial-parallel serial) CCD (charge-coupled device) register. Unlike the most conventional SPS CCD register, this technique deals with charge inputting to and outputting from two selectable channels by buffering the charge transfers at both the serial to parallel and parallel to serial charge transfer stages.