Polysilicon Base Etched Transistor
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
A low diffusion capacitance, high gain structure, reduced collector to base capacitance and increased device density bipolar integrated circuit is described. A method is described below to achieve all of the above goals in a relatively simple manner. 1. Process wafers up to and including deep trench isolation 10 and shallow isolation 12 between the base and collector reach-through regions using conventional technology, as shown in Fig. 1. 2. Deposit a layer 14 of SiO(2) having about 300 nanometers in thickness. 3. Etch areas where polysilicon base contacts are to be formed using reactive ion etching (RIE). 4. Deposit a layer 16 of P+ doped polysilicon of 300 nanometers in thickness using in-situ doped or to be doped by ion implantation. 5.