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Soft Clock Stop

IP.com Disclosure Number: IPCOM000045847D
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07

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Chilinski, H Getzlaff, KJ Hajdu, J Richter, S [+details]


In microprogram-controlled processors, there are several operation modes for program debugging. In addition to the run mode there is generally an instruction step mode (ISM) and an address compare mode (ACM). In the ISM, only one instruction is executed after actuation of the start key START. Subsequently, the processor status can be observed. In the ACM, actuation of START causes a number of instructions to be executed until the address in the control storage address register (CSAR) and the compare value in the compare address register (CA-REG) match, which is determined by comparer (COMP). Then, the processor status is again observed.