Three State Device and Circuit Testing
Original Publication Date: 1983-Apr-01
Included in the Prior Art Database: 2005-Feb-07
Logic devices and circuits containing three-state or push-pull elements may have failure modes that are normally untestable. The present article shows a technique for providing complete testability of such circuits and devices without imposing performance or power consumption penalties. The approach shown also eliminates the possibility of damage to circuits during test.