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Browse Prior Art Database

Inhibiting Cache Loading

IP.com Disclosure Number: IPCOM000045921D
Original Publication Date: 1983-May-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Duke, AH Hartung, MH Huntley, JD Nolan, KP [+details]

Abstract

A peripheral storage hierarchy has a volatile cache backed by a plurality of retentive direct-access storage devices (DASDs). When the host is building a chain of peripheral commands for the storage hierarchy that involves addresses spread randomly across a large set of DASD storage tracks, or a large data set is to be transferred and transfers optimized to DASD, or the references in the chain of command consist of nothing but a series of data writes, then the cache is inhibited from being loaded by any command in the chain. The cache may contain data related to data transfers in the chain. Subsequent to the chain, all data in the cache that is pinned to the cache is updated from the DASD.