Browse Prior Art Database

Specialized Two at a Time Processor

IP.com Disclosure Number: IPCOM000045967D
Original Publication Date: 1983-May-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Pomerene, JH Puzak, TR Rechtschaffen, RN [+details]

Abstract

Described herein is a method whereby processor performance can be improved if BC/BCR (Branch on Condition/Branch on Condition Register) instructions are suppressed.