LSSD Scan Path Truncated to Minimum Length for Testing
Original Publication Date: 1983-May-01
Included in the Prior Art Database: 2005-Feb-07
A design technique called Level Sensitive Scan Design (LSSD) is commonly used today in the design of VLSI logic structures. One advantage of LSSD is in simplifying test generation by making each shift register latch (SRL) memory element a scannable test point, but one result of this is large test data volume since the data to be scanned in and out must accompany each test pattern.