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Frequency Doubler Exclusive-Or Circuit

IP.com Disclosure Number: IPCOM000046019D
Original Publication Date: 1983-May-01
Included in the Prior Art Database: 2005-Feb-07

Publishing Venue

IBM

Related People

Authors:
Bernstein, K [+details]

Abstract

The circuit shown in the figure executes in mimimum power and logic the doubling of an input frequency with designer control over pulse widths and relative positions. The circuit uses both the rising and falling edges of the input signal. This design is especially useful where minimum skew is essential, and tracking with parameter variation is required. Because the generator times its own pulses, the need for any kind of decoding of control signals is eliminated. The generator output levels are fully TTL and FET compatible.